1. Field of the Invention
The present invention relates to delta-sigma modulators and in particular to multi-bit delta-sigma modulators that employ spectral shaping of circuit errors in internal digital-to-analog converters.
2. Description of the Related Art
Over-sampling delta-sigma modulators are widely used in prior art to achieve high-resolution analog-to-digital conversion despite using a coarse quantizer. FIG. 1 depicts a functional block diagram of a typical second order delta-sigma modulator 100 comprising: a first summation circuit 110 for subtracting a first feedback signal (or global feedback signal) f1(n) from a modulator input signal x(n); a first integrator 120 having a transfer function of approximately 0.5z−1/(1-z−1) for integrating an output of the first summation circuit 110; a second summation circuit 130 for subtracting a second feedback signal f2(n) from an output of the first integrator 120; a second integrator 140 having a transfer function of approximately 2z−1/(1-z−1) for integrating an output of the second summation circuit 130; an N-bit quantizer (e.g., analog-to-digital converter or ADC) 150 for digitizing an output of the second integrator 140 into an N-bit modulator output signal y(n); a first N-bit digital-to-analog converter (or DAC) 170 for converting y(n) into the first feedback signal f1(n); and a second N-bit DAC 160 for converting y(n) into the second feedback signal f2(n).
Throughout this disclosure, “(n)” is used to denote a timing index of states or signals of a discrete-time system. When a sampling rate of a modulator input signal x(n) is much higher than a bandwidth of the information of interest, a delta-sigma modulator can spectrally shape its quantization error and greatly suppress its power in the frequency band of interest. Therefore, the delta-sigma modulator can have a high in-band signal-to-quantization-noise-ratio (SQNR) despite using a coarse quantization (i.e., using a small N for the quantizer 150, the second DAC 160 and the first DAC 170 in FIG. 1). The number of integrators used in a delta-sigma modulator determines an order of the modulator. In general, a higher order modulator allows more aggressive spectral shaping, and thus a better in-band SQNR, but has more instability.
In the early days of the history of delta-sigma modulators, 1-bit data conversion (i.e., N=1 for the quantizer 150, the second DAC 160 and the first DAC 170 in FIG. 1) was widely used. This is because 1-bit data conversion is inherently linear and relatively simple as far as circuit design is concerned. In high-order modulators, however, using single-bit data conversion has many drawbacks (e.g., small usable input range, conditional stability and spurious tonal behavior). The drawbacks can all be greatly alleviated by using multi-bit data conversion (i.e., using N>1). For an ideal N-bit DAC, there are 2N output levels that are uniformly spaced. In practice, however, these 2N output levels cannot be perfectly uniformly spaced due to mismatches among circuit elements under a limited tolerance in manufacturing. The non-uniformity (or alternatively described as non-linearity) of a DAC used in a delta-sigma modulator results in a source of circuit errors, which unlike the quantization error, cannot be effectively suppressed by the delta-sigma modulator.
While there have been many works in the prior art that address the problem of circuit errors in a multi-bit DAC used in a delta-sigma modulator, these works generally involve extensive usage of complex digital algorithms. As a result, they are not highly amenable to very high-speed applications. What is needed is a simple digital algorithm to effectively suppress the circuit errors caused by the non-linearity of a multi-bit DAC in a delta-sigma modulator.